BibTeX record conf/memsys/SrikanthSSCW18

download as .bib file

@inproceedings{DBLP:conf/memsys/SrikanthSSCW18,
  author       = {Sriseshan Srikanth and
                  Lavanya Subramanian and
                  Sreenivas Subramoney and
                  Thomas M. Conte and
                  Hong Wang},
  editor       = {Bruce L. Jacob},
  title        = {Tackling memory access latency through {DRAM} row management},
  booktitle    = {Proceedings of the International Symposium on Memory Systems, {MEMSYS}
                  2018, Old Town Alexandria, VA, USA, October 01-04, 2018},
  pages        = {137--147},
  publisher    = {{ACM}},
  year         = {2018},
  url          = {https://doi.org/10.1145/3240302.3240314},
  doi          = {10.1145/3240302.3240314},
  timestamp    = {Thu, 14 Oct 2021 10:05:38 +0200},
  biburl       = {https://dblp.org/rec/conf/memsys/SrikanthSSCW18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.