BibTeX record conf/memocode/PetersPWD16

• > Home > conf/memocode/PetersPWD16

@inproceedings{DBLP:conf/memocode/PetersPWD16,
  author       = {Judith Peters and
                  Nils Przigoda and
                  Robert Wille and
                  Rolf Drechsler},
  title        = {Clocks vs. instants relations: Verifying {CCSL} time constraints in
                  {UML/MARTE} models},
  booktitle    = {2016 {ACM/IEEE} International Conference on Formal Methods and Models
                  for System Design, {MEMOCODE} 2016, Kanpur, India, November 18-20,
                  2016},
  pages        = {78--84},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/MEMCOD.2016.7797750},
  doi          = {10.1109/MEMCOD.2016.7797750},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/memocode/PetersPWD16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}