A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study.

Steve Haynal Timothy Kam Michael Kishinevsky Emily Shriver Xinning Wang A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. 79-88 2008 MEMOCODE http://dx.doi.org/10.1109/MEMCOD.2008.4547693 conf/memocode/2008 db/conf/memocode/memocode2008.html#HaynalKKSW08