BibTeX record conf/lascas/KesslerBRPC22

• > Home > conf/lascas/KesslerBRPC22

@inproceedings{DBLP:conf/lascas/KesslerBRPC22,
  author       = {Henrique Kessler and
                  Murilo Bohlke and
                  Leomar S. da Rosa and
                  Marcelo Schiavon Porto and
                  Vinicius V. Camargo},
  title        = {Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power
                  Supergate Design},
  booktitle    = {13th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
                  2022, Puerto Varas, Chile, March 1-4, 2022},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/LASCAS53948.2022.9789079},
  doi          = {10.1109/LASCAS53948.2022.9789079},
  timestamp    = {Mon, 26 Jun 2023 20:46:40 +0200},
  biburl       = {https://dblp.org/rec/conf/lascas/KesslerBRPC22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}