BibTeX record conf/itc/ZilicR01

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@inproceedings{DBLP:conf/itc/ZilicR01,
  author       = {Zeljko Zilic and
                  Katarzyna Radecka},
  title        = {: Identifying redundant gate replacements in verification by error
                  modeling},
  booktitle    = {Proceedings {IEEE} International Test Conference 2001, Baltimore,
                  MD, USA, 30 October - 1 November 2001},
  pages        = {803--812},
  publisher    = {{IEEE} Computer Society},
  year         = {2001},
  url          = {https://doi.org/10.1109/TEST.2001.966702},
  doi          = {10.1109/TEST.2001.966702},
  timestamp    = {Thu, 23 Mar 2023 23:58:40 +0100},
  biburl       = {https://dblp.org/rec/conf/itc/ZilicR01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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