A novel architecture for on-chip path delay measurement.

Xiaoxiao Wang Mohammad Tehranipoor Ramyanshu Datta A novel architecture for on-chip path delay measurement. 1-10 2009 ITC http://dx.doi.org/10.1109/TEST.2009.5355742 conf/itc/2009 db/conf/itc/itc2009.html#WangTD09