Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.

Manfred Stadler Thomas Röwer Hubert Kaeslin Norbert Felber Wolfgang Fichtner Markus Thalmann Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. 414-420 1999 conf/itc/1999 ITC db/conf/itc/itc1999.html#StadlerRKFFT99