A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.

Narumi Sakashita Fumihiro Okuda Ken'ichi Shimomura Hiroki Shimano Mitsuhiro Hamada Tetsuo Tada Shinji Komori Kazuo Kyuma Akihiko Yasuoka Haruhiko Abe A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. 319-324 1996 conf/itc/1996 ITC db/conf/itc/itc1996.html#SakashitaOSSHTKKYA96