Using on-chip test pattern compression for full scan SoC designs.

Helmut Lang Jens Pfeiffer Jeff Maguire Using on-chip test pattern compression for full scan SoC designs. 638-643 2000 conf/itc/2000 ITC db/conf/itc/itc2000.html#LangPM00 http://doi.ieeecomputersociety.org/10.1109/TEST.2000.894258