Enhanced Delay Test Generator for High-Speed Logic LSIs.

Kazumi Hatayama Mitsuji Ikeda Terumine Hayashi Masahiro Takakura Kuniaki Kishida Shun Ishiyama Enhanced Delay Test Generator for High-Speed Logic LSIs. 161-165 1989 conf/itc/1989 ITC db/conf/itc/itc1989.html#HatayamaIHTKI89