A scalable architecture for VLSI test.

Ed Chang David Cheung Robert E. Huston Jim Seaton Gary Smith A scalable architecture for VLSI test. 500-506 1998 conf/itc/1998 ITC http://www.computer.org/proceedings/itc/5093/50930500abs.htm db/conf/itc/itc1998.html#ChangCHSS98