Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.

B. Bailey A. Metayer B. Svrcek Nandu Tendolkar E. Wolf Eric Fiene Mike Alexander Rick Woltenberg Rajesh Raina Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. 574-583 2002 conf/itc/2002 ITC http://csdl.computer.org/comp/proceedings/itc/2002/7543/00/75430574abs.htm db/conf/itc/itc2002.html#BaileyMSTWFAWR02