BibTeX record: conf/isvlsi/ZhouYZC11

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@inproceedings{DBLP:conf/isvlsi/ZhouYZC11,
  author    = {Shuzhe Zhou and
               Hailong Yao and
               Qiang Zhou and
               Yici Cai},
  title     = {Minimization of Circuit Delay and Power through Gate Sizing and Threshold
               Voltage Assignment},
  booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
               July 2011, Chennai, India},
  pages     = {212--217},
  year      = {2011},
  crossref  = {DBLP:conf/isvlsi/2011},
  url       = {http://dx.doi.org/10.1109/ISVLSI.2011.29},
  doi       = {10.1109/ISVLSI.2011.29},
  timestamp = {Sun, 21 Aug 2011 21:23:14 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/isvlsi/ZhouYZC11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2011,
  title     = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
               July 2011, Chennai, India},
  publisher = {{IEEE} Computer Society},
  year      = {2011},
  timestamp = {Sun, 21 Aug 2011 21:23:14 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/isvlsi/2011},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}