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BibTeX record conf/isvlsi/WuHHW18
@inproceedings{DBLP:conf/isvlsi/WuHHW18, author = {Chia{-}Cheng Wu and Kung{-}Han Ho and Juinn{-}Dar Huang and Chun{-}Yao Wang}, title = {Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays}, booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018, Hong Kong, China, July 8-11, 2018}, pages = {257--262}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/ISVLSI.2018.00055}, doi = {10.1109/ISVLSI.2018.00055}, timestamp = {Fri, 24 Mar 2023 00:02:41 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/WuHHW18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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