A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology.

Chua-Chin Wang Gang-Neng Sung A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. 405-410 2006 conf/isvlsi/2006 ISVLSI http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.5 db/conf/isvlsi/isvlsi2006.html#WangS06