Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits.

Saraju P. Mohanty Ramakrishna Velagapudi Valmiki Mukherjee Hao Li Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. 248-249 2005 conf/isvlsi/2005 ISVLSI http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.62 db/conf/isvlsi/isvlsi2005.html#MohantyVML05