Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.

Zhipeng Liu Jinian Bian Qiang Zhou Hui Dai Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. 279-284 2007 conf/isvlsi/2007 ISVLSI http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.60 db/conf/isvlsi/isvlsi2007.html#LiuBZD07