default search action
BibTeX record conf/isvlsi/JiangL18
@inproceedings{DBLP:conf/isvlsi/JiangL18, author = {Iris Hui{-}Ru Jiang and Pei{-}Yu Lee}, title = {Timing Macro Modeling for Efficient Hierarchical Timing Analysis}, booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018, Hong Kong, China, July 8-11, 2018}, pages = {714}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/ISVLSI.2018.00134}, doi = {10.1109/ISVLSI.2018.00134}, timestamp = {Fri, 24 Mar 2023 00:02:42 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/JiangL18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.