Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.

Peter Celinski Said F. Al-Sarawi Derek Abbott Sorin Cotofana Stamatis Vassiliadis Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. 127-134 2004 conf/isvlsi/2004 ISVLSI http://csdl.computer.org/comp/proceedings/isvlsi/2004/2097/00/20970127abs.htm db/conf/isvlsi/isvlsi2004.html#CelinskiAACV04