BibTeX record conf/issoc/FindenigE10

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@inproceedings{DBLP:conf/issoc/FindenigE10,
  author       = {Rainer Findenig and
                  Wolfgang Ecker},
  title        = {State chart refinement validation from approximately timed to cycle
                  callable models},
  booktitle    = {2010 International Symposium on System on Chip, SoC 2010, Tampere,
                  September 29-30, 2010},
  pages        = {72--75},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSOC.2010.5625551},
  doi          = {10.1109/ISSOC.2010.5625551},
  timestamp    = {Mon, 09 Aug 2021 14:54:02 +0200},
  biburl       = {https://dblp.org/rec/conf/issoc/FindenigE10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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