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BibTeX record conf/isscc/WangYCLY07
@inproceedings{DBLP:conf/isscc/WangYCLY07, author = {Ping{-}Ying Wang and Meng{-}Ta Yang and Shang{-}Ping Chen and Meng{-}Hsueh Lin and Jing{-}Bing Yang}, title = {RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction}, booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC} 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007}, pages = {254--600}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/ISSCC.2007.373390}, doi = {10.1109/ISSCC.2007.373390}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isscc/WangYCLY07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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