<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/isscc/RamezaniASIRMHPSCS11" mdate="2011-09-30">
<author>Mehrdad Ramezani</author>
<author>Mohamed Abdalla</author>
<author>Ayal Shoval</author>
<author>Marcus Van Ierssel</author>
<author>Afshin Rezayee</author>
<author>Angus McLaren</author>
<author>Chris D. Holdenried</author>
<author>Jennifer Pham</author>
<author>Eric So</author>
<author>David Cassan</author>
<author>Saman Sadr</author>
<title>An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology.</title>
<pages>352-354</pages>
<year>2011</year>
<booktitle>ISSCC</booktitle>
<ee>http://dx.doi.org/10.1109/ISSCC.2011.5746350</ee>
<crossref>conf/isscc/2011</crossref>
<url>db/conf/isscc/isscc2011.html#RamezaniASIRMHPSCS11</url>
</inproceedings>
</dblp>
