BibTeX record conf/isscc/NoguchiITAKKHAS16

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@inproceedings{DBLP:conf/isscc/NoguchiITAKKHAS16,
  author       = {Hiroki Noguchi and
                  Kazutaka Ikegami and
                  Satoshi Takaya and
                  Eishi Arima and
                  Keiichi Kushida and
                  Atsushi Kawasumi and
                  Hiroyuki Hara and
                  Keiko Abe and
                  Naoharu Shimomura and
                  Junichi Ito and
                  Shinobu Fujita and
                  Takashi Nakada and
                  Hiroshi Nakamura},
  title        = {7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization
                  and write-verify-write / read-modify-write scheme},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {132--133},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417942},
  doi          = {10.1109/ISSCC.2016.7417942},
  timestamp    = {Fri, 22 Mar 2024 08:49:46 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/NoguchiITAKKHAS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}