BibTeX record conf/isscc/LinNSYLCHLLHTANYGSJWJWCWCCWC24

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@inproceedings{DBLP:conf/isscc/LinNSYLCHLLHTANYGSJWJWCWCCWC24,
  author       = {Ku{-}Feng Lin and
                  Hiroki Noguchi and
                  Yi{-}Chun Shih and
                  Perng{-}Fei Yuh and
                  Yuan{-}Jen Lee and
                  Tung{-}Cheng Chang and
                  Sheng{-}Po Huang and
                  Yu{-}Fan Lin and
                  Chun{-}Ying Lee and
                  Yen{-}Hsiang Huang and
                  Jui{-}Che Tsai and
                  Saman Adham and
                  Peter Noel and
                  Ramin Yazdi and
                  Marat Gershoig and
                  YangJae Shin and
                  Vineet Joshi and
                  Ted Wong and
                  Meng{-}Ru Jiang and
                  J. J. Wu and
                  Chun{-}Tai Cheng and
                  Yu{-}Jen Wang and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Yih Wang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {15.9 {A} 16nm 16Mb Embedded {STT-MRAM} with a 20ns Write Time, a 10\({}^{\mbox{12}}\)
                  Write Endurance and Integrated Margin-Expansion Schemes},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
                  San Francisco, CA, USA, February 18-22, 2024},
  pages        = {292--294},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ISSCC49657.2024.10454339},
  doi          = {10.1109/ISSCC49657.2024.10454339},
  timestamp    = {Tue, 07 May 2024 20:09:08 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LinNSYLCHLLHTANYGSJWJWCWCCWC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}