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BibTeX record conf/isscc/LeeCLLPOJJCLYCOMPCKYKJKLJPKKOKJKKKYYL24
@inproceedings{DBLP:conf/isscc/LeeCLLPOJJCLYCOMPCKYKJKLJPKKOKJKKKYYL24, author = {Jinhyung Lee and Kyungjun Cho and Chang Kwon Lee and Yeonho Lee and Jae{-}Hyung Park and Su{-}Hyun Oh and Yucheon Ju and Chunseok Jeong and Ho Sung Cho and Jaeseung Lee and Tae{-}Sik Yun and Jin Hee Cho and Sangmuk Oh and Junil Moon and Young{-}Jun Park and Hong{-}Seok Choi and In{-}Keun Kim and Seung Min Yang and Sun{-}Yeol Kim and Jaemin Jang and Jinwook Kim and Seong{-}Hee Lee and Younghyun Jeon and Juhyung Park and Tae{-}Kyun Kim and Dongyoon Ka and Sanghoon Oh and Jinse Kim and Junyeol Jeon and Seonhong Kim and Kyeong Tae Kim and Taeho Kim and Hyeonjin Yang and Dongju Yang and Minseop Lee and Heewoong Song and Dongwook Jang and Junghyun Shin and Hyunsik Kim and Chang{-}Ki Baek and Hajun Jeong and Jongchan Yoon and Seung{-}Kyun Lim and Kyo Yun Lee and Young Jun Koo and Myeong{-}Jae Park and Joohwan Cho and Jonghwan Kim}, title = {13.4 {A} 48GB 16-High 1280GB/s {HBM3E} {DRAM} with All-Around Power {TSV} and a 6-Phase {RDQS} Scheme for {TSV} Area Optimization}, booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024, San Francisco, CA, USA, February 18-22, 2024}, pages = {238--240}, publisher = {{IEEE}}, year = {2024}, url = {https://doi.org/10.1109/ISSCC49657.2024.10454440}, doi = {10.1109/ISSCC49657.2024.10454440}, timestamp = {Tue, 09 Apr 2024 17:11:43 +0200}, biburl = {https://dblp.org/rec/conf/isscc/LeeCLLPOJJCLYCOMPCKYKJKLJPKKOKJKKKYYL24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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