Stop the war!
Остановите войну!
for scientists:
default search action
BibTeX record conf/isscc/KimKCALCPPJKCYJ21
@inproceedings{DBLP:conf/isscc/KimKCALCPPJKCYJ21, author = {Yong{-}Hun Kim and Hyung{-}Jin Kim and Jaemin Choi and Min{-}Su Ahn and Dongkeon Lee and Seung{-}Hyun Cho and Dong{-}Yeon Park and Young{-}Jae Park and Min{-}Soo Jang and Yong{-}Jun Kim and Jinyong Choi and Sung{-}Woo Yoon and Jae{-}Woo Jung and Jae{-}Koo Park and Jae{-}Woo Lee and Dae{-}Hyun Kwon and Hyung{-}Seok Cha and Si{-}Hyeong Cho and Seong{-}Hoon Kim and Jihwa You and Kyoung{-}Ho Kim and Dae{-}Hyun Kim and Byung{-}Cheol Kim and Young{-}Kwan Kim and Jun{-}Ho Kim and Seouk{-}Kyu Choi and Chanyoung Kim and Byongwook Na and Hye{-}In Choi and Reum Oh and Jeong{-}Don Ihm and Seung{-}Jun Bae and Nam Sung Kim and Jung{-}Bae Lee}, title = {25.2 {A} 16Gb Sub-1V 7.14Gb/s/pin {LPDDR5} {SDRAM} Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an {FSS} Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3\({}^{\mbox{rd}}\)-Generation 10nm {DRAM}}, booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021, San Francisco, CA, USA, February 13-22, 2021}, pages = {346--348}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/ISSCC42613.2021.9366050}, doi = {10.1109/ISSCC42613.2021.9366050}, timestamp = {Sun, 30 Jul 2023 09:43:20 +0200}, biburl = {https://dblp.org/rec/conf/isscc/KimKCALCPPJKCYJ21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.