BibTeX record conf/isscc/HaraguchiFYCHCNWC24

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@inproceedings{DBLP:conf/isscc/HaraguchiFYCHCNWC24,
  author       = {Masaru Haraguchi and
                  Yorinobu Fujino and
                  Yoshisato Yokoyama and
                  Ming{-}Hung Chang and
                  Yu{-}Hao Hsu and
                  Hong{-}Chen Cheng and
                  Koji Nii and
                  Yih Wang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {15.3 {A} 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write
                  Pseudo-2-Port {SRAM} with Folded-Bitline Multi-Bank Architecture},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
                  San Francisco, CA, USA, February 18-22, 2024},
  pages        = {280--282},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ISSCC49657.2024.10454463},
  doi          = {10.1109/ISSCC49657.2024.10454463},
  timestamp    = {Tue, 07 May 2024 20:09:09 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/HaraguchiFYCHCNWC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}