BibTeX record conf/isscc/ChenCG21

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@inproceedings{DBLP:conf/isscc/ChenCG21,
  author       = {Zhengyu Chen and
                  Xi Chen and
                  Jie Gu},
  title        = {15.3 {A} 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro
                  and {CNN} Accelerator with Retention Enhancement, Adaptive Analog
                  Sparsity and 44TOPS/W System Energy Efficiency},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {240--242},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9366045},
  doi          = {10.1109/ISSCC42613.2021.9366045},
  timestamp    = {Fri, 11 Nov 2022 08:02:55 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ChenCG21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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