BibTeX record conf/isqed/YelamarthiC08

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@inproceedings{DBLP:conf/isqed/YelamarthiC08,
  author       = {Kumar Yelamarthi and
                  Chien{-}In Henry Chen},
  title        = {Process Variation Aware Timing Optimization through Transistor Sizing
                  in Dynamic {CMOS} Logic},
  booktitle    = {9th International Symposium on Quality of Electronic Design {(ISQED}
                  2008), 17-19 March 2008, San Jose, CA, {USA}},
  pages        = {143--147},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISQED.2008.4479715},
  doi          = {10.1109/ISQED.2008.4479715},
  timestamp    = {Thu, 23 Mar 2023 23:58:32 +0100},
  biburl       = {https://dblp.org/rec/conf/isqed/YelamarthiC08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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