@inproceedings{DBLP:conf/isqed/VenkatramanCTMR09,
  author    = {R. Venkatraman and
               R. Castagnetti and
               Andres Teene and
               Benjamin Mbouombouo and
               S. Ramesh},
  title     = {Power {\&} variability test chip architecture and 45nm-generation
               silicon-based analysis for robust, power-aware SoC design},
  booktitle = {ISQED},
  year      = {2009},
  pages     = {27-32},
  ee        = {http://dx.doi.org/10.1109/ISQED.2009.4810265},
  crossref  = {DBLP:conf/isqed/2009},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/isqed/2009,
  title     = {10th International Symposium on Quality of Electronic Design
               (ISQED 2009), 16-18 March 2009, San Jose, CA, USA},
  booktitle = {ISQED},
  publisher = {IEEE},
  year      = {2009},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}