<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/isqed/RomaDSPP05" mdate="2006-01-04">
<author>Carlo Roma</author>
<author>Pierluigi Daglio</author>
<author>Guido De Sandre</author>
<author>Marco Pasotti</author>
<author>Marco Poles</author>
<title>How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.</title>
<pages>107-112</pages>
<year>2005</year>
<crossref>conf/isqed/2005</crossref>
<booktitle>ISQED</booktitle>
<ee>http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.62</ee>
<url>db/conf/isqed/isqed2005.html#RomaDSPP05</url>
</inproceedings>
</dblp>
