A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.

Prasun Raha Scott Randall Richard Jennings Bob Helmick Ajith Amerasekera Baher Haroun A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. 148- 2002 ISQED http://computer.org/proceedings/isqed/1561/15610148abs.htm db/conf/isqed/isqed2002.html#RahaRJHAH02