Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.

Ing-Chao Lin Suresh Srinivasan Narayanan Vijaykrishnan Nagu R. Dhanwada Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. 775-780 2006 conf/isqed/2006 ISQED http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.138 db/conf/isqed/isqed2006.html#LinSVD06