Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.

Ming-Dou Ker Wen-Yu Lo Tung-Yang Chen Howard Tang S.-S. Chen M.-C. Wang Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. 267-272 2001 conf/isqed/2001 ISQED http://csdl.computer.org/comp/proceedings/isqed/2001/1025/00/10250267abs.htm db/conf/isqed/isqed2001.html#KerLCTCW01