Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.

Praveen Elakkumanan Kishan Prasad Ramalingam Sridhar Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. 617-624 2006 conf/isqed/2006 ISQED http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.137 db/conf/isqed/isqed2006.html#ElakkumananPS06