Akira Yamawaki Masahiko Iwane Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. 324-333 2005 ISPAN http://doi.ieeecomputersociety.org/10.1109/ISPAN.2005.27 conf/ispan/2005 db/conf/ispan/ispan2005.html#YamawakiI05