BibTeX record conf/ispan/ChalasaniTC94

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@inproceedings{DBLP:conf/ispan/ChalasaniTC94,
  author       = {Prasad R. Chalasani and
                  Krishnaiyan Thulasiraman and
                  M. A. Corneau},
  title        = {Integrated {VLSI} layout compaction and wire balancing on a shared
                  memory multiprocessor: evaluation of a parallel algorithm},
  booktitle    = {International Symposium on Parallel Architectures, Algorithms and
                  Networks, {ISPAN} 1994, Kanazawa, Japan, December 14-16, 1994},
  pages        = {49--56},
  publisher    = {{IEEE} Computer Society},
  year         = {1994},
  url          = {https://doi.org/10.1109/ISPAN.1994.367165},
  doi          = {10.1109/ISPAN.1994.367165},
  timestamp    = {Fri, 24 Mar 2023 00:03:18 +0100},
  biburl       = {https://dblp.org/rec/conf/ispan/ChalasaniTC94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}