BibTeX record conf/ispacs/LaiCCS21

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@inproceedings{DBLP:conf/ispacs/LaiCCS21,
  author       = {Jin{-}Yang Lai and
                  Chiung{-}An Chen and
                  Shih{-}Lun Chen and
                  Chun{-}Yu Su},
  title        = {Implement 32-bit {RISC-V} Architecture Processor using Verilog {HDL}},
  booktitle    = {International Symposium on Intelligent Signal Processing and Communication
                  Systems, {ISPACS} 2021, Hualien City, Taiwan, November 16-19, 2021},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISPACS51563.2021.9651130},
  doi          = {10.1109/ISPACS51563.2021.9651130},
  timestamp    = {Wed, 12 Jan 2022 09:10:25 +0100},
  biburl       = {https://dblp.org/rec/conf/ispacs/LaiCCS21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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