BibTeX record conf/ispacs/AdionoAPDPS16

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@inproceedings{DBLP:conf/ispacs/AdionoAPDPS16,
  author       = {Trio Adiono and
                  Mahendra Drajat Adhinata and
                  Novi Prihatiningrum and
                  Ricky Disastra and
                  Rachmad Vidya Wicaksana Putra and
                  Amy Hamidah Salman},
  title        = {An architecture design of {SAD} based template matching for fast queue
                  counter in {FPGA}},
  booktitle    = {International Symposium on Intelligent Signal Processing and Communication
                  Systems, {ISPACS} 2016, Phuket, Thailand, October 24-27, 2016},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISPACS.2016.7824708},
  doi          = {10.1109/ISPACS.2016.7824708},
  timestamp    = {Wed, 16 Oct 2019 14:14:51 +0200},
  biburl       = {https://dblp.org/rec/conf/ispacs/AdionoAPDPS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}