Ben A. Abderazek Soichi Shigeta Tsutomu Yoshinaga Masahiro Sowa On the Design of a Register Queue Based Processor Architecture (FaRM-rq). 248-262 http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2745&spage=248 2003 conf/ispa/2003 ISPA db/conf/ispa/ispa2003.html#AbderazekSYS03