BibTeX record conf/isocc/WangH16

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@inproceedings{DBLP:conf/isocc/WangH16,
  author       = {Chua{-}Chin Wang and
                  Chia{-}Lung Hsieh},
  title        = {Disturb-free 5T loadless {SRAM} cell design with multi-vth transistors
                  using 28 nm {CMOS} process},
  booktitle    = {International SoC Design Conference, {ISOCC} 2016, Jeju, South Korea,
                  October 23-26, 2016},
  pages        = {103--104},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISOCC.2016.7799754},
  doi          = {10.1109/ISOCC.2016.7799754},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isocc/WangH16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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