Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors.

Jing Shen Motoi Inaba Koichi Tanno Okihiko Ishizuka Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. 15-20 2000 ISMVL http://computer.org/proceedings/ismvl/0692/06920015abs.htm db/conf/ismvl/ismvl2000.html#ShenITI00