Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.

Soo Jin Park Byoung Hee Yoon Kwang Sub Yoon Heung Soo Kim Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. 198-203 2004 conf/ismvl/2004 ISMVL http://csdl.computer.org/comp/proceedings/ismvl/2004/2130/00/21300198abs.htm db/conf/ismvl/ismvl2004.html#ParkYYK04