BibTeX record conf/ismvl/KawahitoMIN92

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@inproceedings{DBLP:conf/ismvl/KawahitoMIN92,
  author       = {Shoji Kawahito and
                  Y. Mitsui and
                  Makoto Ishida and
                  Tetsuro Nakamura},
  title        = {Parallel Hardware Algorithms with Redundant Number Representations
                  for Multiple-Valued Arithmetic {VLSI}},
  booktitle    = {22nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
                  1992, Sendai, Japan, May 27-29, 1992, Proceedings},
  pages        = {337--345},
  publisher    = {{IEEE} Computer Society},
  year         = {1992},
  url          = {https://doi.org/10.1109/ISMVL.1992.186815},
  doi          = {10.1109/ISMVL.1992.186815},
  timestamp    = {Thu, 23 Mar 2023 23:59:57 +0100},
  biburl       = {https://dblp.org/rec/conf/ismvl/KawahitoMIN92.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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