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BibTeX record conf/islped/YoshimotoTUOKSMMKY12
@inproceedings{DBLP:conf/islped/YoshimotoTUOKSMMKY12, author = {Shusuke Yoshimoto and Masaharu Terada and Youhei Umeki and Shunsuke Okumura and Atsushi Kawasumi and Toshikazu Suzuki and Shinichi Moriwaki and Shinji Miyano and Hiroshi Kawaguchi and Masahiko Yoshimoto}, editor = {Naresh R. Shanbhag and Massimo Poncino and Pai H. Chou and Ajith Amerasekera}, title = {A 40-nm 256-Kb Sub-10 pJ/Access 8t {SRAM} with read bitline amplitude limiting {(RBAL)} scheme}, booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, {USA} - July 30 - August 01, 2012}, pages = {85--90}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2333660.2333683}, doi = {10.1145/2333660.2333683}, timestamp = {Mon, 11 Mar 2024 15:42:29 +0100}, biburl = {https://dblp.org/rec/conf/islped/YoshimotoTUOKSMMKY12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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