A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.

Hiroyuki Yamauchi Toru Iwata Hironori Akamatsu Akira Matsuzawa A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. 49-54 1996 conf/islped/1996 ISLPED http://doi.acm.org/10.1145/252493.252571 db/conf/islped/islped1996.html#YamauchiIAM96