BibTeX record conf/islped/WangXG16

download as .bib file

@inproceedings{DBLP:conf/islped/WangXG16,
  author       = {Huanyu Wang and
                  Geng Xie and
                  Jie Gu},
  title        = {Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency
                  in Voltage Scalable Design},
  booktitle    = {Proceedings of the 2016 International Symposium on Low Power Electronics
                  and Design, {ISLPED} 2016, San Francisco Airport, CA, USA, August
                  08 - 10, 2016},
  pages        = {22--27},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2934583.2934584},
  doi          = {10.1145/2934583.2934584},
  timestamp    = {Tue, 02 Mar 2021 16:17:22 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/WangXG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.