BibTeX record conf/islped/ShinKLS13

• > Home > conf/islped/ShinKLS13

@inproceedings{DBLP:conf/islped/ShinKLS13,
  author       = {Insup Shin and
                  Jae{-}Joon Kim and
                  Yu{-}Shiang Lin and
                  Youngsoo Shin},
  editor       = {Pai H. Chou and
                  Ru Huang and
                  Yuan Xie and
                  Tanay Karnik},
  title        = {A pipeline architecture with 1-cycle timing error correction for low
                  voltage operations},
  booktitle    = {International Symposium on Low Power Electronics and Design (ISLPED),
                  Beijing, China, September 4-6, 2013},
  pages        = {199--204},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISLPED.2013.6629294},
  doi          = {10.1109/ISLPED.2013.6629294},
  timestamp    = {Thu, 06 Jun 2024 10:53:08 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/ShinKLS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}