BibTeX record conf/islped/NarayananPL98

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@inproceedings{DBLP:conf/islped/NarayananPL98,
  author       = {Unni Narayanan and
                  Peichen Pan and
                  C. L. Liu},
  editor       = {Anantha P. Chandrakasan and
                  Sayfe Kiaei},
  title        = {Low power logic synthesis under a general delay model},
  booktitle    = {Proceedings of the 1998 International Symposium on Low Power Electronics
                  and Design, 1998, Monterey, California, USA, August 10-12, 1998},
  pages        = {209--214},
  publisher    = {{ACM}},
  year         = {1998},
  url          = {https://doi.org/10.1145/280756.280900},
  doi          = {10.1145/280756.280900},
  timestamp    = {Mon, 27 Sep 2021 11:47:11 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/NarayananPL98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}