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BibTeX record conf/islped/NakataOKY10
@inproceedings{DBLP:conf/islped/NakataOKY10, author = {Yohei Nakata and Shunsuke Okumura and Hiroshi Kawaguchi and Masahiko Yoshimoto}, editor = {Vojin G. Oklobdzija and Barry Pangle and Naehyuck Chang and Naresh R. Shanbhag and Chris H. Kim}, title = {0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid {SRAM}}, booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010}, pages = {219--224}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1840845.1840888}, doi = {10.1145/1840845.1840888}, timestamp = {Mon, 11 Mar 2024 15:42:29 +0100}, biburl = {https://dblp.org/rec/conf/islped/NakataOKY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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